The present invention relates to a power amplifier in a cellular phone unit that uses two or more frequency bands, and more particularly to a method for reducing the threshold of an FET used in a bias circuit.
A current mirror circuit is a circuit for controlling and passing a current determined by an FET size ratio with respect to a reference current IREF. FIG. 1 is a circuit diagram showing the configuration of a typical current mirror circuit.
A constant current I1 in the current mirror circuit is expressed by the following equation.I1=β×(VG1−Vth)2  (1)
where β denotes a coefficient, VG1 denotes the gate terminal voltage of the current mirror circuit, and Vth denotes the threshold voltage of the FET configuring the current mirror circuit. The coefficient β is expressed by the following equation.
                    β        ⁢                                  ∝                              W            L                    ⁢          μ          ⁢                                          ⁢                      C            ox                                              (        2        )            
where W denotes the gate width of the FET in FIG. 1, L denotes a gate length, μ denotes a mobility, and Cox denotes an oxide film capacitance.
By modifying equation (1), the gate terminal voltage VG1 is expressed as follows.
                              V                                    G              ⁢                                                          ⁢              1                        ⁢                                                                =                                                            I                1                            β                                +                      V            th                                              (        3        )            
From these relations, a transconductance gm1 can be obtained as follows.
                              gm          1                =                              2            ×            β            ×                          (                                                V                                      G                    ⁢                                                                                  ⁢                    1                                                  -                                  V                  th                                            )                                =                      2            ×                          β                        ×                                          (                                  I                  1                                )                                            1                2                                                                        (        4        )            
With the past bias method expressed by the above equations, it is theoretically possible to control an accurate transconductance by controlling the amount of current.
However, in reality, a drain modulation effect shown in FIG. 2 is produced on the FET. FIG. 2 is a graph showing the drain modulation effect of the FET.
The drain modulation effect refers to the phenomenon that the conductance increases in proportion to the gate voltage as the thickness of an inversion layer between the source and the drain increases in proportion to the gate voltage.
In the graph of FIG. 2, the horizontal axis represents a source-drain voltage VDS, and the vertical axis represents a current ID flowing through a drain terminal. In the graph of FIG. 2, ideal values are indicated by solid lines, and actual measurement values are indicated by broken lines.
As is obvious from FIG. 2, in theory, the FET should maintain a constant current in the saturation region. However, in reality, the source-drain current ID is affected by a gate-drain voltage and increases proportionally. In FIG. 2, the difference between points B and C is the difference between theoretical and actual values.
A current ID based on the actual measurement values is expressed by the following equation.ID=β×(VG1−Vth)2×(1+λVDS)  (5)
where VDS denotes a drain-source voltage, and λ denotes a drain modulation coefficient.
From the foregoing, a transconductance is derived as follows.
                                                        gm              =                            ⁢                              2                ×                β                ×                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                                              V                        DS                                                                              )                                ×                                  (                                                            V                                              G                        ⁢                                                                                                  ⁢                        1                                                              -                                          V                      th                                                        )                                                                                                        =                            ⁢                              2                ×                β                ×                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                                              V                        DS                                                                              )                                ×                                                                            I                      D                                                                                                  β                      ×                                              (                                                  1                          +                                                      λ                            ⁢                                                                                                                  ⁢                                                          V                              DS                                                                                                      )                                                                                                                                                                    =                            ⁢                              2                ×                                                      β                    ×                                          (                                              1                        +                                                  λ                          ⁢                                                                                                          ⁢                                                      V                            DS                                                                                              )                                                                      ×                                                      I                    D                                                                                                          (        6        )            
There have been proposed various modification methods for the ideal values and actual measurement values.
Past known devices include a cascode current mirror circuit. This is designed to cancel the drain modulation effect by equalizing the source-drain voltages of an FET to which the reference current IREF is inputted and an FET which outputs a current equal to the reference current IREF. The use the cascode current mirror circuit is known as described in International Publication WO2009/037762A1.